This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-231646, filed on Aug. 8, 2002, the entire contents of which are incorporated herein by reference.
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device provided with a power down mode that stops refreshing, which is performed to retain data, while activating an internal power supply.
A dynamic random access memory (DRAM) is often used in lieu of a static random access memory (SRAM) in portable electronic devices, such as a cellular phone. A system including a DRAM periodically refreshes the memory cells of the DRAM to retain data. Recent DRAM systems enter a first standby state in which data retention is required and a second standby state in which data retention is not required. The refreshing of the DRAM in the second standby state consumes current in an unnecessary manner. To reduce power consumption in the second standby state, a DRAM provided with a power down mode, which includes a refresh stop mode (nap mode) and a sleep mode, has been developed. The refresh stop mode inactivates circuits required for refreshing. The sleep mode stops the supply of internal power.
FIG. 1 is a schematic block diagram showing a prior art DRAM 60, which is provided with a power down mode. The DRAM 60 includes a self-refresh control circuit 61, a power down control circuit 62, an internal power generation circuit 63, a refresh control circuit 64, a main circuit 65, and a NOR circuit 70.
The self-refresh control circuit 61, which includes an OSC control circuit 66, an oscillation circuit 67, a cycle counter 68, and a request generation circuit 69, generates a refresh request signal req in a predetermined cycle.
The OSC control circuit 66 includes a PMOS transistor TP1 and a resistor R1, which are connected in series between a power supply and the ground. The gate terminal of the PMOS transistor TP1 is connected to its drain terminal, from which an oscillation frequency control signal VR is output. The control signal VR is set by the current (constant current) I that flows through the PMOS transistor TP1 and the resistor R1. It is preferred that the current I be relatively small to perform a low current consumption operation. For example, the resistor R1 has 10 Mxcexa9 and the current I has several microamperes (e.g., 1 microampere).
The oscillation circuit 67 includes an odd number (three in FIG. 1) of inverter circuits 71, 72, 73, which are connected in a looped manner to configure a ring oscillator. The power supply terminals of the inverter circuits 71 to 73 are respectively connected to the power supply via PMOS transistors TP2, TP3, and TP4. The gate terminals of the PMOS transistors TP2 to TP4 are provided with the oscillation frequency control signal VR. The transistors TP2 to TP4 supply the inverter circuits 71 to 73 with control current in accordance with the control signal VR. The ring oscillator, which is configured by the inverter circuits 71 and 73, functions in this manner to produce an oscillation signal OSC. The oscillation signal OSC is provided to the cycle counter 68. The cycle counter 68 counts the pulse number of the oscillation signal to determine a refresh cycle. The request generation circuit 69 outputs a request signal req in each refresh cycle, which is determined by the cycle counter 68.
The power down control circuit 62 determines whether an external signal (not shown) represents a power down mode to generate a nap mode entry signal NAPe or a sleep mode entry signal SLEEPe.
The NOR circuit 70 has a first input terminal, which is provided with the request signal req from the request generation circuit 69, and a second input terminal, which is provided with the entry signal NAPe of the nap mode from the power down control circuit 62.
The NOR circuit 70 provides the refresh control circuit 64 with the request signal req. The refresh control circuit 64 controls self-refresh in response to the request signal req.
The main circuit 65 includes a DRAM core 65a, which includes a memory cell array, a row decoder, a column decoder, and a sense amplifier. The refresh control circuit 64 activates each word line in the DRAM core 65a and refreshes the data stored in the memory cells connected to the activated word line.
The internal power generation circuit 63 generates power supply voltage, which is supplied to the DRAM core 65a and its peripheral circuits, and internal power, such as the negative potential supplied to the substrate to activate the DRAM 60 or a boosting potential. In other words, the internal power generation circuit 63 generates power supply voltage for operating the self-refresh control circuit 61, the main circuit 65, and the refresh control circuit 64. The power down control circuit 62 provides the internal power generation circuit 63 with the sleep mode entry signal SLEEPe. This inactivates the power generation circuit 63, stops the generation of the power supply voltage, and stops the refresh operation of the memory cells. The power supply voltage for operating the power down control circuit 62 is generated by another internal power generation circuit (not shown).
The operation of the DRAM 60 will now be discussed.
(Nap Mode)
When the entry signal NAPe provided from the power down control circuit 62 to the NOR circuit 70 has a high level (the nap period between time t11 to time t12 in FIG. 2), the NOR circuit 70 continuously outputs a signal having a low level. Thus, the refresh control circuit 64 is not provided with the request signal req. This stops the refresh operation of the memory cells and reduces current consumption. In the nap mode, the internal power generation circuit 63 is activated as shown in the state of FIG. 3. Thus, the refresh control circuit 64, the main circuit 65, and the self-refresh control circuit 61 are supplied with power. In this state, the entry signal NAPe of the power down control circuit 62 stops providing the refresh control circuit 64 with the request signal req from the self-refresh control circuit 61 to stop the refresh operation.
(Sleep Mode)
Referring to FIG. 4, when the power down control circuit 62 provides the internal power generation circuit 63 with the entry signal SLEEPe, the internal power generation circuit 63 stops generating power. In this state, the power down control circuit 62 breaks a power line that connects the internal power generation circuit 63 to an external power supply and an internal power line that connects the internal power generation circuit 63 to the circuits 61, 64, and 65.
FIG. 5 illustrates the current consumption in a normal standby mode, the nap mode, and the sleep mode.
In the nap mode, the AC current of the refresh operation is decreased from the current consumption in the normal standby mode. In the sleep mode, the AC current of the oscillation operation in the self-refresh control circuit (self-control circuit) 61 and the DC current of the internal power generation circuit 63 are decreased from the current consumption in the nap mode. That is, in the sleep mode, circuits other than the power down (PD) control circuit 62 (i.e., the circuit required to determine the mode) are disconnected from the power supply and inactivated to reduce current consumption.
Referring to FIG. 6A, during the sleep mode period (sleep period from time t11 to time t12), the internal power generation circuit 63 is inactivated and the internal power voltage is decreased to the ground voltage. Thus, a recovery time (time t12 to t13) of several hundred microseconds is necessary to return the mode to the normal standby mode from the sleep mode and to activate the internal power generation circuit 63 and stabilize the internal power voltage.
Referring to FIG. 6B, during the nap mode period (nap period from time t11 to time t12), the internal power generation circuit 63 is activated. Thus, the mode quickly returns to the normal standby mode from the nap mode. Accordingly, the use of the nap mode is optimal when frequently shifting between an operation mode that requires data retention and an operation mode that does not require data retention.
As described above, in the nap mode, the request signal req is not provided to stop the refresh operation. However, the oscillation circuit 67 and the OSC control circuit 66 of the self-refresh control circuit 61 are continuously activated for the reasons described below.
The oscillation circuit 67 constantly performs the oscillation operation in an asynchronous manner when the internal power generation circuit 63 is activated. Thus, if the oscillation operation of the oscillation circuit 67 is interrupted and subsequently restarted, the oscillation signal OSC would have a cycle that differs from the predetermined oscillation cycle. This may result of erroneous functioning of the refresh control circuit 64. More specifically, if the cycle counter 68 were to perform a count operation in accordance with an oscillation signal OSC having a cycle that differs from the predetermined cycle, the cycle of the request signal req would differentiate from the desired refresh cycle.
The OSC control circuit 66 includes the resistor RI, which has a high resistance. Thus, if the power supply to the OSC control circuit 66 were cut, a predetermined time would be necessary for the oscillation frequency control signal VR to reach a predetermined value when the power supply is started. The oscillation signal OSC that has an oscillation frequency differing from the predetermined frequency is generated during a transition period (instable period) during which the oscillation frequency control signal VR reaches a predetermined value. However, unnecessary current is consumed by stopping only the request signal req to operate the OSC control circuit 66 and the oscillation circuit 67 during the nap mode.
An aspect of the present invention is a semiconductor memory device, which performs refreshing for data retention, provided with a power down mode that stops refreshing. The device includes an oscillation circuit for generating an oscillation signal. A request generation circuit generates a refresh request signal with the oscillation signal of the oscillation circuit, wherein the oscillation circuit stops generation of the oscillation signal in response to a power down mode entry signal.
A further aspect of the present invention is a semiconductor memory device including a power down control circuit for generating a power down mode entry signal. A refresh control circuit generates a refresh request signal for the semiconductor memory device. The refresh control circuit includes an oscillation circuit for generating an oscillation signal. An oscillation control circuit is connected to the oscillation circuit to generate a control signal for controlling the frequency of the oscillation signal. A cycle counter counts the oscillation signal of the oscillation circuit. A request generation circuit is connected to the cycle counter to generate the refresh request signal in accordance with a count value. The oscillation circuit stops generation of the oscillation signal in response to the power down mode entry signal.
A further aspect of the present invention is a method for controlling a semiconductor memory device provided with a normal mode, in which refreshing is periodically performed, and a power down mode, in which refreshing is stopped. The semiconductor memory device includes a refresh control circuit for performing an oscillation operation and generating a refresh request signal. The method comprising the steps of shifting the mode from the normal mode to the power down mode, stopping the generation of the refresh request signal by stopping the oscillation operation of the refresh control circuit during the power down mode, returning the mode from the power down mode to the normal mode, and generating the refresh request signal by starting the oscillation operation of the refresh control circuit during the normal mode.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.